Integrated circuits, and more particularly integrated circuit packaging techniques are well known in the art. One packaging technique referred to as flip chip bonding is particularly suited for use in devices having moderately high I/O count. With flip chip bonding, an integrated circuit is bonded directly to a package substrate with solder/bumps carried on the integrated circuit metalization. The package substrate, which is usually multi-layered, includes layers of conductive patterns which makes selective contact with the solder/bumps through vias in the substrate. Flip chip bonding is desirable due to lowered power supply distribution impedance and resulting lowered supply voltage noise. However, flip chip bonding can be expensive. This cost is driven, in important part, by very high routing density demands placed on the package substrate.
Wire bonding is another well known packaging technique. Here, the integrated circuit includes a plurality of bonding pads. The package substrate also includes bonding pads. The bonding pads of the integrated circuit are wire bonded to the package substrate bonding pads. Wire bonding is generally a low cost technique. It places significantly less demands on packaging substrate routing density.
There are many low cost applications where flip chip bonding would not be an economically viable bonding technique while wire bonding would be an economically viable bonding technique. However, many of these applications would benefit from the advantages of flip chip bonding in terms of power distribution throughout the integrated circuit. The present invention addresses this issue by providing a low cost integrated circuit having the advantages of both flip chip bonding and wire bonding.